Intel VT-x Basics: VMX Modes and Core Virtualization Concepts
Intel VT-x is the core of Intel's hardware-assisted virtualization. It adds VMX root and VMX non-root operation modes and uses the VMCS structure to hold VM state. These basics are the essential path to understanding the VT Debugger.
Core Concepts
VMX Operation Modes
VMX root mode hosts the VMM (hypervisor); VMX non-root mode hosts the guest. Both have four privilege levels, but in non-root mode privileged instruction behavior is governed by the VMCS.
VMXON / VMXOFF
VMXON enters VMX operation and VMXOFF leaves it. Before entering, CR4.VMXE must be set and a VMXON region prepared.
VMCS (Virtual Machine Control Structure)
A hardware-maintained memory region holding guest state, host state and execution-control fields. The VMM accesses it via VMREAD/VMWRITE.
VM-entry / VM-exit
VMLAUNCH/VMRESUME cause VM-entry into the guest; when the guest executes a controlled instruction or event, a VM-exit occurs and the CPU saves guest state and loads host state.
VM-exit Reasons
Every VM-exit carries a 32-bit reason code (e.g., #UD, EPT violation, CPUID, CR access) that the VMM dispatches on.
EPT & VPID
EPT translates guest-physical to host-physical addresses; VPID keeps per-vCPU TLB entries to avoid flushes after VM-exits.
Key Code
; 进入 VMX 操作的最小流程（汇编示意）
mov eax, cr4
or eax, 0x2000 ; CR4.VMXE = 1
mov cr4, eax
vmxon [vmxon_region] ; 进入 VMX root 模式
mov eax, vmcs_region
vmptrld eax ; 加载当前 VMCS
; 填充 guest/host 状态后:
vmlaunch ; 首次进入客户机（VM-entry）
; 发生 VM-exit 后回到这里，检查 VMCS 退出原因
vmread eax, [exit_reason_field]Structure Cheat Sheet
| VMXON Region | 4KB-aligned region used when entering VMX operation |
|---|---|
| VMCS Region | 4KB-aligned structure holding VM state, with guest/host state areas |
| VMREAD/VMWRITE | Instructions that read/write VMCS fields by encoding |
| VMLAUNCH | First entry into the guest (launches the VMCS) |
| VMRESUME | Re-entry into the guest (resumes the VMCS) |
| CR4.VMXE | VMX enable bit; must be set before VMXON |
| INVEPT/INVVPID | Instructions that invalidate EPT caches or VPID TLBs |
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