AMD-Vi IOMMU: Device Virtualization and DMA Isolation

AMD-Vi is AMD's IOMMU, handling device DMA address translation and interrupt remapping. It is key to device passthrough and a hardware barrier against DMA attacks.

Core Concepts

DMA Remapping

DMA addresses seen by devices are translated by the IOMMU to real physical addresses, preventing arbitrary memory access.

Device Passthrough

Assigning a physical device directly to a VM lets the guest driver drive it at near-native performance.

Interrupt Remapping

Mapping device MSI/MSI-X safely to guest virtual interrupts, preventing interrupt injection attacks.

IVHD Structures

IVHD entries in the ACPI IVRS table describe IOMMU capabilities and device sets, parsed at boot.

Security Value

Enabling the IOMMU blocks direct memory access (DMA) attacks such as hardware keyloggers and PCIe exploits.

Working with SVM

SVM virtualizes the CPU and AMD-Vi virtualizes I/O; together they form AMD's full virtualization stack.

Key Code

# 检查 Linux 下 AMD-Vi 是否启用
        dmesg | grep -i -E "AMD-Vi|IOMMU"
        # 预期输出类似:
        # AMD-Vi: AMD IOMMUv2 functionality not available ...
        # AMD-Vi: Lazy IO/TLB flushing enabled
        # 内核参数启用(/etc/default/grub):
        # GRUB_CMDLINE_LINUX="... iommu=pt amd_iommu=on"

Structure Cheat Sheet

DMA 重映射Device DMA address → physical address translation
中断重映射MSI/MSI-X → guest virtual interrupt mapping
设备直通Assigning a physical device directly to a guest
IVRS 表ACPI table describing IOMMU configuration
DMA 防护Blocks arbitrary memory access from malicious devices

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